Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems) - Image 1

£77.19

Artech House Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)

Name: Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)
Brand: Artech House
Price: 77.19 GBP
Availability: InStock

Circuits

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£77 today · previous high £77 · all-time low £46

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Description

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Specifications

Brand: Artech House
Format: hardcover
ASIN: 1596939893
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering > Circuits
Domain: Amazon UK
Release Date: 31 March 2010
Listed Since: 12 October 2009

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Artech House Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)

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