£130.16

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£130 today · all-time low £127 (Sep 2026) · usually £129

Springer Formal Equivalence Checking and Design Debugging - Springer

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Description

Formal Equivalence Checking and Design Debugging is a comprehensive guide to two essential areas of design verification: logic equivalence checking and design debugging. The first section examines the design problems that necessitate logic equivalence checking and explores the foundational technologies employed to address them, including novel approaches for verifying design revisions following intensive sequential transformations such as retiming. The second section provides an in-depth survey of both established and contemporary literature on design error diagnosis and design error correction, making this volume an invaluable resource for engineers and researchers working in electronic testing and verification methodologies.

Key Features

Covers logic equivalence checking and design debugging as core topics within formal verification and electronic design validation.

Details novel approaches to verifying design revisions after sequential transformations including retiming techniques.

Provides comprehensive survey of design error diagnosis and correction methodologies from foundational and recent research.

Part of Springer's Frontiers in Electronic Testing series, volume 12, offering peer-reviewed expertise in design verification.

Product Specifications

Format
paperback
Domain
Amazon UK
Publication Date
30 September 2012
Listed Since
12 December 2012

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No barcode data available

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