£129.86

Springer Formal Equivalence Checking and Design Debugging

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Description

Master the complexities of design verification with Formal Equivalence Checking and Design Debugging. Published by Springer as part of the Frontiers in Electronic Testing series, this book provides a deep dive into two essential topics: logic equivalence checking and design debugging. The first section of this text examines the specific design problems that necessitate logic equivalence checking. It explains the underlying technologies used to resolve these issues and offers detailed descriptions of new approaches for verifying design revisions. This is particularly useful for managing intensive sequential transformations like retiming. The second section provides a comprehensive survey of both historical and recent literature regarding design error diagnosis and correction. Whether you are researching design error diagnosis or looking for modern verification technologies, this volume serves as a technical resource for understanding how to maintain design integrity through rigorous checking and debugging processes.

Key Features

Covers two major topics in design verification: logic equivalence checking and design debugging.

Explains the underlying technologies used to solve specific design problems requiring logic equivalence checking.

Provides detailed descriptions of novel approaches for verifying design revisions after sequential transformations like retiming.

Includes a thorough survey of previous and recent literature on design error diagnosis and correction.

Part of the Frontiers in Electronic Testing series (Volume 12) from Springer.

Product Specifications

Format
Paperback
Domain
Amazon UK
Publication Date
30 September 2012
Listed Since
12 December 2012

Barcode

No barcode data available

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