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£131.35
Springer Formal Equivalence Checking and Design Debugging
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Description
Key Features
Covers two major topics in design verification: logic equivalence checking and design debugging.
Explains the underlying technologies used to solve specific design problems requiring logic equivalence checking.
Provides detailed descriptions of novel approaches for verifying design revisions after sequential transformations like retiming.
Includes a thorough survey of previous and recent literature on design error diagnosis and correction.
Part of the Frontiers in Electronic Testing series (Volume 12) from Springer.
Product Specifications
- Brand
- Springer
- Format
- paperback
- ASIN
- 1461376068
- Domain
- Amazon UK
- Publication Date
- 30 September 2012
- Listed Since
- 12 December 2012
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