£75.40

Springer Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog

Price data last checked 93 day(s) ago - refreshing...

View at Amazon

We'll watch every seller, every day. One email when your price arrives.

About as cheap as it gets. The only time it was cheaper was 2 years ago.

£75 today · all-time low £72 (Jun 2024) · usually the usual

NEW HERE?

Amazon shows you one price. We show you all of them.

Tosheroon watches Amazon prices so you don't have to. Every product on Amazon has a price history — we make it visible. Set the price you'd actually pay, and we'll email you the second it gets there. No app, no account, one email.

WHAT'S ON THIS PAGE

↓ Price chart
when this has been cheap or pricey
↓ Forecast
where the price is heading next
↓ Statistics
all-time high & low, recent range
↑ Price alert
name your number, we'll email you

Price History & Forecast

Grey patches = out of stock. Cheaper = lower on the chart. Hover for exact prices.

Last 638 days • 638 data points (No recent data available)

Historical
Generating forecast...
£89.99 £70.70 £74.91 £79.12 £83.32 £87.53 £91.74 09 June 2024 15 November 2024 23 April 2025 29 September 2025 08 March 2026

Price Distribution

Price distribution over 638 days • 4 price levels

Days at Price
Current Price
392 days 106 days 136 days · current 4 days 0 98 196 294 392 £73 £74 £75 £90 Days at Price

Price Analysis

Most common price: £73 (392 days, 61.4%)

Price range: £73 - £90

Price levels: 4 different prices over 638 days

Description
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

Product Specifications
Brand
Springer
Format
paperback
ASIN
1475773137
Category
Books > Subjects > Computing & Internet > Computer Science > Architecture & Microprocessors
Domain
Amazon UK
Publication Date
12 April 2013
Listed Since
22 September 2013

Barcode

No barcode data available

Similar Products You Might Like

Logic Design and Verification Using SystemVerilog (Revised)
97% match

Logic Design and Verification Using SystemVerilog (Revised)

CREATESPACE

£49.47 12 Jan 2026
Formal Verification: An Essential Toolkit for Modern VLSI Design
97% match

Formal Verification: An Essential Toolkit for Modern VLSI Design

Morgan Kaufmann

£68.64 25 Jan 2026
Writing Testbenches using SystemVerilog
97% match

Writing Testbenches using SystemVerilog

Springer

£155.97 20 Jan 2026
SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
97% match

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Springer

£79.98 22 Jan 2026
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
97% match

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

CREATESPACE

£88.42 25 Jan 2026
Digital VLSI Design and Simulation with Verilog
97% match

Digital VLSI Design and Simulation with Verilog

Wiley

£88.19 09 Mar 2026
Applied Formal Verification: For Digital Circuit Design (ELECTRONICS)
97% match

Applied Formal Verification: For Digital Circuit Design (ELECTRONICS)

McGraw-Hill Education

£111.99 07 Mar 2026
SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
97% match

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Springer

£45.56 01 Feb 2026
Assertion-Based Design
97% match

Assertion-Based Design

Springer

£78.46 03 Mar 2026
Principles of Verilog Digital Design
97% match

Principles of Verilog Digital Design

£54.37 09 Jan 2026
SystemVerilog for Hardware Description: RTL Design and Verification
97% match

SystemVerilog for Hardware Description: RTL Design and Verification

Springer

£61.59 17 Mar 2026
SystemVerilog for Hardware Description: RTL Design and Verification
97% match

SystemVerilog for Hardware Description: RTL Design and Verification

Springer

£79.93 24 Jan 2026
Scalable Hardware Verification with Symbolic Simulation
97% match

Scalable Hardware Verification with Symbolic Simulation

Springer

£57.40 23 Feb 2026
Digital Logic Design Using Verilog: Coding and RTL Synthesis
97% match

Digital Logic Design Using Verilog: Coding and RTL Synthesis

Springer

£111.19 12 Apr 2026
Verification Methodology Manual for SystemVerilog
97% match

Verification Methodology Manual for SystemVerilog

Springer

£85.01 02 Mar 2026
Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
97% match

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

Springer

£118.03 11 Jan 2026
Post-Silicon and Runtime Verification for Modern Processors
97% match

Post-Silicon and Runtime Verification for Modern Processors

Springer

£106.78 09 Apr 2026
Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
96% match

Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them

Springer

£105.50 11 Mar 2026
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
96% match

Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)

Morgan Kaufmann

£59.77 14 Apr 2026
SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
96% match

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

Springer

£111.90 25 Feb 2026
Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
96% match

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute

Springer

£86.34 08 Apr 2026
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability (IEEE Press)
96% match

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability (IEEE Press)

Wiley

£116.88 25 Jan 2026
Functional Verification of Dynamically Reconfigurable FPGA-based Systems
96% match

Functional Verification of Dynamically Reconfigurable FPGA-based Systems

Springer

£75.84 07 Mar 2026
SystemVerilog Assertions Handbook Revised 4 th edition 2023: … for Dynamic and Formal Verification
96% match

SystemVerilog Assertions Handbook Revised 4 th edition 2023: … for Dynamic and Formal Verification

£79.53 06 Feb 2026