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Springer Digital Timing Macromodeling for VLSI Design Verification

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Description

Digital Timing Macromodeling for VLSI Design Verification is a comprehensive technical resource that traces the evolution of simulation techniques in digital circuit design. This book delivers detailed coverage of circuit simulation, timing analysis, fast-timing methods, switch-level timing, and gate-level simulation approaches used in modern VLSI verification. It examines mixed-mode simulation strategies and interconnection analysis methods, providing engineers with comparative insights into the advantages and disadvantages of different macromodeling techniques. Part of the Springer International Series in Engineering and Computer Science (volume 319), this reference work equips designers and verification specialists with the knowledge needed to select and implement appropriate simulation methodologies for complex digital systems.

Key Features

Comprehensive history and development overview of digital simulation techniques for VLSI design verification.

Detailed examination of circuit simulation, timing simulation, fast-timing, and switch-level timing methodologies.

Analysis of gate-level simulation approaches and mixed-mode simulation integration strategies.

Coverage of interconnection analysis methods essential for accurate digital macromodeling.

Part of the Springer International Series in Engineering and Computer Science, volume 319, establishing academic credibility.

Product Specifications

Format
paperback
Domain
Amazon UK
Publication Date
03 October 2012
Listed Since
14 July 2013

Barcode

No barcode data available

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