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Springer ASIC/SoC Functional Design Verification Guide

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Description

Master the complexities of semiconductor design with this comprehensive guide from Springer. This book provides the necessary technologies and methodologies to build a functional design verification strategy and environment. It is designed to help engineers guarantee first-pass working silicon by addressing the toughest challenges in the field. The text begins with a high-level overview of verification sub-fields, providing enough depth for engineers to grasp the landscape before moving into technical specifics. Readers will gain detailed knowledge of industry standard technologies, including Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), SystemVerilog Functional Coverage (SFC), and Coverage Driven Verification (CDV). This resource serves as a technical roadmap for creating robust verification environments in modern ASIC and SoC design.

Key Features

This Springer publication covers all required technologies and methodologies to create a functional design verification strategy.

Learn to build environments that help guarantee first-pass working silicon for ASIC and SoC projects.

The guide provides a high-level overview of verification sub-fields to help engineers grasp the industry landscape.

Detailed technical instruction is provided for industry standard technologies like UVM and SystemVerilog Assertions (SVA).

Gain expertise in SystemVerilog Functional Coverage (SFC) and Coverage Driven Verification (CDV) methodologies.

Product Specifications

Format
hardcover
Domain
Amazon UK
Release Date
07 July 2017
Listed Since
20 April 2017

Barcode

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