Springer SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Digital VLSI Design and Simulation with Verilog

Wiley

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

Springer

PLD Based Design with VHDL: RTL Design, Synthesis and Implementation

Springer

Analog Behavioral Modeling with the Verilog-A Language

Springer

VHDL: Analysis and Modeling of Digital Systems

McGraw-Hill Education

Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog

Springer

Formal Verification: An Essential Toolkit for Modern VLSI Design

Morgan Kaufmann

Digital Logic Design Using Verilog: Coding and RTL Synthesis

Springer

SystemVerilog for Hardware Description: RTL Design and Verification

Springer

VHDL for Logic Synthesis

Wiley-Blackwell

Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

Springer

Design of Digital Systems and Devices: 79 (Lecture Notes in Electrical Engineering, 79)

Springer

Embedded Microprocessor System Design using FPGAs

Springer

Reconfigurable System Design and Verification

CRC Press

Functional Verification of Dynamically Reconfigurable FPGA-based Systems

Springer

Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them

Springer

Enhanced Virtual Prototyping: Featuring RISC-V Case Studies

Springer

Next Level Testbenches: Design Patterns in SystemVerilog and UVM

Next Level Testbenches: Design Patterns in SystemVerilog and UVM

Digital Design and Computer Architecture

Morgan Kaufmann

SVA: The Power of Assertions in SystemVerilog

Springer