£73.10

Springer Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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£73.10 £64.25 £66.18 £68.11 £70.04 £71.97 £73.91 05 February 2026 27 February 2026 21 March 2026 12 April 2026 04 May 2026

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3 days 19 days 11 days 55 days 1 day · current 0 14 28 41 55 £65 £69 £70 £73 £73 Days at Price

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Most common price: £73 (55 days, 61.8%)

Price range: £65 - £73

Price levels: 5 different prices over 89 days

Description

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Product Specifications

Format
hardcover
Domain
Amazon UK
Release Date
02 December 2013
Listed Since
15 August 2013

Barcode

No barcode data available

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