£65.02

Springer Designing 2D and 3D Network-on-Chip Architectures

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£79.99 £62.62 £66.41 £70.20 £73.99 £77.78 £81.57 19 December 2024 07 April 2025 25 July 2025 11 November 2025 01 March 2026

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Description

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies. From the Back Cover This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

Product Specifications

Format
Paperback
Domain
Amazon UK
Release Date
23 August 2016
Listed Since
04 August 2016

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No barcode data available

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