£109.19

Wiley Verilog Coding for Logic Synthesis - Engineering Text

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Description

Master the practical aspects of Verilog design with this comprehensive guide from Wiley. This book is designed to help engineers and students move beyond theory by focusing on the actual design problems encountered in daily professional practice. By prioritizing real-world application, it serves as an essential resource for anyone looking to strengthen their RTL coding and verification skills. Whether you are a student in an EE department or a working professional, this text provides a clear path to understanding complex digital systems. It covers the entire design lifecycle, from initial specification and architectural definition to micro-architectural definition and testbench coding. This structured approach ensures that learners can follow the logic from a concept to a fully verified design. It is an ideal textbook for VLSI courses and a reliable reference for digital design engineers.

Key Features

Practical design approach that focuses on the types of problems design engineers solve on a daily basis.

Includes over 90 design examples to provide extensive practice and diverse scenarios for learners.

Features 3 full scale design examples covering specification, architecture, RTL coding, and verification.

Comprehensive workflow instruction including architectural definition, micro-architectural definition, and testbench coding.

Designed as a suitable textbook for EE departments teaching VLSI courses and digital logic design.

Product Specifications

Brand
Wiley
Format
hardcover
Domain
Amazon UK
Release Date
13 May 2003
Listed Since
17 October 2006

Barcode

No barcode data available

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