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Wiley Verilog Coding for Logic Synthesis - Wiley

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Description

Master practical Verilog design with this comprehensive guide from Wiley that bridges theory and real-world engineering challenges. Packed with over 90 design examples, this book equips you with the hands-on knowledge needed for logic synthesis and RTL coding. Three complete design case studies walk you through every stage - from specification and architectural planning to micro-architectural definition, RTL implementation, testbench development and verification testing. Whether you're a design engineer tackling daily synthesis problems or a student in a VLSI course, this textbook provides the practical framework and proven techniques for successful Verilog-based digital design and problem solving.

Key Features

Over 90 practical design examples demonstrating real-world Verilog coding techniques for logic synthesis applications.

Three full-scale design case studies covering complete workflows from specification through architectural and micro-architectural definition to RTL coding and verification.

Testbench coding and verification instruction integrated throughout the Verilog design examples for comprehensive validation understanding.

Suitable as a textbook for EE departments offering VLSI courses, making it valuable for both academic and professional learning environments.

Product Specifications

Brand
Wiley
Format
hardcover
Domain
Amazon UK
Release Date
13 May 2003
Listed Since
17 October 2006

Barcode

No barcode data available

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