£69.00

LAP Lambert Academic Publishing Minimization of Dynamic Power Through Structural Changes &Vt Techniques: low power cmos circuits

Price data last checked 20 day(s) ago - will refresh soon

View at Amazon

We'll watch every seller, every day. One email when your price arrives.

It has never been this cheap. We have no record of a lower price.

£69 today · cheaper than every other day in the last 3 months

NEW HERE?

Amazon shows you one price. We show you all of them.

Tosheroon watches Amazon prices so you don't have to. Every product on Amazon has a price history — we make it visible. Set the price you'd actually pay, and we'll email you the second it gets there. No app, no account, one email.

WHAT'S ON THIS PAGE

↓ Price chart
when this has been cheap or pricey
↓ Forecast
where the price is heading next
↓ Statistics
all-time high & low, recent range
↑ Price alert
name your number, we'll email you

Price History & Forecast

Grey patches = out of stock. Cheaper = lower on the chart. Hover for exact prices.

Last 71 days · 71 data points (no recent data)

Historical
Generating forecast…
£69.00 £65.55 £66.93 £68.31 £69.69 £71.07 £72.45 08 July 2026 25 July 2026 12 August 2026 29 August 2026 16 September 2026

Price Distribution

Price distribution over 71 days • 1 price levels

Days at Price
71 days 0 18 36 53 71 £69 Days at Price

Price Analysis

Most common price: £69 (71 days, 100.0%)

Price range: £69 - £69

Price levels: 1 different prices over 71 days

Description

Over the past decade, low power, energy efficient Very Large Scale Integration design has been the focal point for active research and development. The rapid technology scaling, growing integration capacity and leakage power dissipation are the contributing factors for increas in the complexity of modern VLSI design. Voltage scaling is one of the most efficient ways for reducing power and energy in VLSI circuitry. Due to the reduced threshold voltage, switching speed becomes faster, active leakage current is increased. A technique to dynamically manage active leakage current, which reduces the energy dissipation in VLSI circuitry at different circuits with different levels of complexity is required. As technology scale into the deep sub micron technology regime, sub threshold leakage power increases exponentially with the reduction of the threshold voltage. Therefore effective leakage and dynamic power minimization techniques become necessary. Ground, power and hybrid gated techniques are proposed as effective circuit level techniques that get better performance, low leakage and low dynamic power. The design and performance evaluation of 1-bi.

Product Specifications

Barcode

No barcode data available

Similar Products You Might Like

Minimizing and Exploiting Leakage in VLSI Design
87% match

Minimizing and Exploiting Leakage in VLSI Design

Springer

£129.99 15 Sep 2026
A Novel LVSD Design and its Robustness to Process Variation Effects: Low Power and Robust Techniques for CMOS Circuits
86% match

A Novel LVSD Design and its Robustness to Process Variation Effects: Low Power and Robust Techniques for CMOS Circuits

LAP Lambert Academic Publishing

£60.00 14 Sep 2026
Low Power Digital CMOS Design
86% match

Low Power Digital CMOS Design

Springer

£114.06 06 Aug 2026
Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies: 25 (Springer Series in Advanced Microelectronics, 25)
86% match

Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies: 25 (Springer Series in Advanced Microelectronics, 25)

Springer

£74.61 04 Aug 2026
Low-Power Variation-Tolerant Design in Nanometer Silicon
85% match

Low-Power Variation-Tolerant Design in Nanometer Silicon

Springer

£80.67 06 Aug 2026
Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design
84% match

Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design

Springer

£80.67 08 Aug 2026
Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems
84% match

Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems

LAP Lambert Academic Publishing

£79.00 27 Aug 2026
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
84% match

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Springer

£48.95 13 Aug 2026
Logic Synthesis for Low Power VLSI Designs
83% match

Logic Synthesis for Low Power VLSI Designs

Springer

£117.49 15 Sep 2026
UNIFICATION OF VLSI PARTITIONING: PLACEMENT AND FLOORPLANNING
83% match

UNIFICATION OF VLSI PARTITIONING: PLACEMENT AND FLOORPLANNING

LAP Lambert Academic Publishing

£52.00 14 Sep 2026
Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits
83% match

Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits

Springer

£103.27 18 Sep 2026
Analysis of Low Power Methodologies for Multiplier: A Low Power Approach
83% match

Analysis of Low Power Methodologies for Multiplier: A Low Power Approach

LAP Lambert Academic Publishing

£71.00 15 Sep 2026
Power-Aware Testing and Test Strategies for Low Power Devices
83% match

Power-Aware Testing and Test Strategies for Low Power Devices

Springer

£103.27 10 Aug 2026
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
82% match

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Springer

£80.67 06 Aug 2026
Low-Voltage CMOS Log Companding Analog Design: 733 (The Springer International Series in Engineering and Computer Science, 733)
82% match

Low-Voltage CMOS Log Companding Analog Design: 733 (The Springer International Series in Engineering and Computer Science, 733)

Springer

£75.68 06 Aug 2026
Low-Voltage CMOS Log Companding Analog Design: 733 (The Springer International Series in Engineering and Computer Science, 733)
82% match

Low-Voltage CMOS Log Companding Analog Design: 733 (The Springer International Series in Engineering and Computer Science, 733)

Springer

£82.80 15 Sep 2026
Modelling of Low Power Accelerometer Interfacing Circuitry: Stability & Analysis
82% match

Modelling of Low Power Accelerometer Interfacing Circuitry: Stability & Analysis

LAP Lambert Academic Publishing

£55.00 14 Sep 2026
CMOS/BiCMOS ULSI: Low Voltage, Low Power (Prentice Hall Modern Semiconductor Design Series)
82% match

CMOS/BiCMOS ULSI: Low Voltage, Low Power (Prentice Hall Modern Semiconductor Design Series)

PEARSON EDUCATION

Price unavailable
Energy Efficient VLSI Design and Implementation on 28nm FPGA: FPGA Based Energy Efficient Register, Memory and ALU Design
82% match

Energy Efficient VLSI Design and Implementation on 28nm FPGA: FPGA Based Energy Efficient Register, Memory and ALU Design

LAP Lambert Academic Publishing

£55.00 27 Aug 2026
Dynamic Power Management: Design Techniques and CAD Tools
82% match

Dynamic Power Management: Design Techniques and CAD Tools

Springer

£108.01 05 Aug 2026
Design and Implementation of a Low-Power SOI CMOS Receiver
82% match

Design and Implementation of a Low-Power SOI CMOS Receiver

LAP Lambert Academic Publishing

£62.00 10 Sep 2026
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits: 387 (The Springer International Series in Engineering and Computer Science, 387)
82% match

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits: 387 (The Springer International Series in Engineering and Computer Science, 387)

Springer

£109.90 07 Aug 2026
Advanced Low-Power Digital Circuit Techniques: 405 (The Springer International Series in Engineering and Computer Science, 405)
81% match

Advanced Low-Power Digital Circuit Techniques: 405 (The Springer International Series in Engineering and Computer Science, 405)

Springer

£108.77 08 Aug 2026
Understanding sub-threshold SCL for ultra-low power application: Sub-threshold logic in the field of low-power digital circuit design
81% match

Understanding sub-threshold SCL for ultra-low power application: Sub-threshold logic in the field of low-power digital circuit design

LAP Lambert Academic Publishing

£43.00 18 Sep 2026