Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems - Image 1

£79.00

LAP Lambert Academic Publishing Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems

Name: Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems
Brand: LAP Lambert Academic Publishing
Price: 79.0 GBP
Availability: InStock

Electronics Engineering

Price data last checked 40 day(s) ago - refreshing...

View at Amazon

We'll watch every seller, every day. One email when your price arrives.

It has never been this cheap. We have no record of a lower price.

£79 today · cheaper than every other day in the last 3 months

NEW HERE?

Amazon shows you one price. We show you all of them.

Tosheroon watches Amazon prices so you don't have to. Every product on Amazon has a price history — we make it visible. Set the price you'd actually pay, and we'll email you the second it gets there. No app, no account, one email.

WHAT'S ON THIS PAGE

↓ Price chart
when this has been cheap or pricey

↓ Forecast
where the price is heading next

↓ Statistics
all-time high & low, recent range

↑ Price alert
name your number, we'll email you

Price History & Forecast

Grey patches = out of stock. Cheaper = lower on the chart. Hover for exact prices.

Last 51 days · 51 data points (no recent data)

Historical

Generating forecast…

Price Distribution

Price distribution over 51 days • 1 price levels

Days at Price

Price Analysis

Most common price: £79 (51 days, 100.0%)

Price range: £79 - £79

Price levels: 1 different prices over 51 days

Description

Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.

Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 6207460421
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Release Date: 20 February 2024
Listed Since: 15 March 2024

Barcode

No barcode data available

LAP Lambert Academic Publishing Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems

It has never been this cheap. We have no record of a lower price.

Price History & Forecast

Price Distribution

Price Analysis

Description

Product Specifications

Barcode

Similar Products You Might Like

VLSI Technology & Testability: Design & Testability

Proektirovanie tsifrovykh ustroystv i sistem: s ispol'zovaniem yazyka VHDL

The Electric Power System Made Simple

Energy Efficient VLSI Design and Implementation on 28nm FPGA: FPGA Based Energy Efficient Register, Memory and ALU Design

VLSI for Video Decoding: Low-cost, Low-power, and Error-Robustness

LOW POWER VLSI DESIGN: SUPERSCALAR PROCESSOR UNIT

Test Infrastructure Design: for Digital, Mixed-Signal and Hierarchical SOCs

Power System Engineering: Transient Analysis

Fundamentals of Power System Protection

Fuzzy Logic Controller: Theory,Design & Application in Power System

Preserving Circuit Breaker Adequacy in Electric Power Systems: Concepts, Implications, and Methodologies

Vospitatel'naya sistema v sovremennom vuze: teoriya i praktika

Pravovye problemy nalogooblozheniya vertikal'nykh integratsionnykh struktur

MODERN POWER TRACING METHODS FOR DEREGULATED POWER SYSTEMS: CONCEPTS, ALGORITHMS AND APPLICATION

Design and Implementation of a Low-Power SOI CMOS Receiver

Dynamic and Steady State power system Stability

Adaptive Digital Predistortion for Power Amplifier Linearization: Second Edition

Analysis and Design of Algorithms

Power Quality Mitigation Techniques For Renewable Energy Systems: Power Quality Mitigation Techniques For Hybrid PV - Wind Power Generation System - Grid Connected

Enhancing the conceptual design phase of complex engineering systems

Dynamic Real Time Optimization for Large Scale Processes

Nanostructured Semiconductor Device Design in Solar Cells

OVERVIEW OF ELECTRICAL POWER QUALITY

Artificial Intelligence and Expert Systems