Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level - Image 1

£68.59

Cambridge University Press Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Name: Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level
Brand: Cambridge University Press
Price: 68.59 GBP
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Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.

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Brand: Cambridge University Press
Format: hardcover
ASIN: 1108494544
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering > Circuits
Domain: Amazon UK
Release Date: 30 January 2020
Listed Since: 18 September 2019

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Cambridge University Press Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

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