Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits - Image 1

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LAP Lambert Academic Publishing Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits

Name: Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
Brand: LAP Lambert Academic Publishing
Price: 50.0 GBP
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Electronics Engineering

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The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.

Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 365951361X
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Publication Date: 26 January 2014
Listed Since: 27 January 2014

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LAP Lambert Academic Publishing Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits

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It has never been this cheap. We have no record of a lower price.

LAP Lambert Academic Publishing Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits

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