Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking - Image 1

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LAP Lambert Academic Publishing Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking

Name: Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking
Brand: LAP Lambert Academic Publishing
Price: 65.0 GBP
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Description

Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the special characteristics of each synthesis sub-task separately. This book is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with data-paths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A high-level synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support hand-in-hand synthesis and verification.

Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 3838398130
Category: Books > Subjects > Computing & Internet
Domain: Amazon UK
Release Date: 30 August 2010
Listed Since: 31 August 2010

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LAP Lambert Academic Publishing Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking

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LAP Lambert Academic Publishing Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking

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