Impact of Leakage Power Reduction Techniques on Parametric Yield: Low-Power Design of Digital Integrated Circuits under Process Parameter Variations - Image 1

£57.00

LAP Lambert Academic Publishing Impact of Leakage Power Reduction Techniques on Parametric Yield: Low-Power Design of Digital Integrated Circuits under Process Parameter Variations

Name: Impact of Leakage Power Reduction Techniques on Parametric Yield: Low-Power Design of Digital Integrated Circuits under Process Parameter Variations
Brand: LAP Lambert Academic Publishing
Price: 57.0 GBP
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Electronics Engineering

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Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 3659273910
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Release Date: 22 January 2013
Listed Since: 23 January 2013

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LAP Lambert Academic Publishing Impact of Leakage Power Reduction Techniques on Parametric Yield: Low-Power Design of Digital Integrated Circuits under Process Parameter Variations

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