High Throughput Low Power Architecture for Network-on-chip: Network-on-Chip - Image 1

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LAP Lambert Academic Publishing High Throughput Low Power Architecture for Network-on-chip: Network-on-Chip

Name: High Throughput Low Power Architecture for Network-on-chip: Network-on-Chip
Brand: LAP Lambert Academic Publishing
Price: 55.0 GBP
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Electronics Engineering

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Description

To keep pace with market demand for more performance and functionality in electronic products like mobile phones, digital cameras, computers and digital televisions, manufacturers pack billions of transistors onto a single chip. Increasing transistor density, higher operating frequencies drive today's semiconductor industry scenery. Under these conditions, there is a desire to create Network-on-Chip (NoC); the implementation and integration of multiple computer or entire electronic systems (microcontroller, memory block, timers, peripherals, etc..) on a single chip. High throughput architecture to achieve high performance NoC is the target for the proposed research. The proposed architecture can also improve the latency of the network. Another proposed research area is to design a low power switch to achieve power-efficient NoC. To the best of our knowledge, this is the first in depth analysis on circuit level to optimize performance of different NoC typologies.

Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 3659232351
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Release Date: 27 September 2012
Listed Since: 30 September 2012

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LAP Lambert Academic Publishing High Throughput Low Power Architecture for Network-on-chip: Network-on-Chip

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It has never been this cheap. We have no record of a lower price.

LAP Lambert Academic Publishing High Throughput Low Power Architecture for Network-on-chip: Network-on-Chip

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