£107.98

Springer - Principles of Verifiable RTL Design in Verilog

Name: Springer - Principles of Verifiable RTL Design in Verilog
Brand: Springer
Price: 107.98 GBP
Availability: InStock

Architecture & Microprocessors

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Description

Principles of Verifiable RTL Design provides a deep look into functional coding styles that support verification processes in Verilog. As digital systems evolve, the methods used to model, specify, simulate, and document these designs must also advance. This book explores the transition from electronic and fabrication-based details to the logical behavior models that define modern digital systems. Following the historical shift initiated by C. E. Shannon in 1948, the focus of digital representation moved toward logic diagrams and Boolean equations. This text addresses the needs of system designers, computer scientists, and engineers who require robust notations for communicating and controlling digital designs. By focusing on a coding style that prioritizes verification, this resource helps professionals bridge the gap between theoretical logic and practical RTL implementation. It is an essential addition for those studying the architecture and microprocessors of modern computing systems.

Key Features

Focuses on functional coding styles specifically designed to support and improve the verification processes in Verilog.

Explores the evolution of digital system representation from fabrication details to logical behavior models.

Provides essential knowledge for system designers, computer scientists, and engineers working with digital systems.

Covers the historical context of digital modeling, including the impact of C. E. Shannon's logical revelations.

Addresses necessary notations for modeling, specifying, simulating, and documenting complex digital designs.

Product Specifications

Brand: Springer
Format: paperback
ASIN: 1475774184
Category: Books > Subjects > Computing & Internet > Computer Science > Architecture & Microprocessors
Domain: Amazon UK
Release Date: 23 March 2013
Listed Since: 18 April 2014

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Springer - Principles of Verifiable RTL Design in Verilog

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