SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE - Image 1

£57.65

VDM Verlag SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE

Name: SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE
Brand: VDM Verlag
Price: 57.65 GBP
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Electronics Engineering

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Increasing the complexity of the electronic systems leads to electronic system level modeling concept supporting hardware and software co-design and co-verification environment in a single framework. SystemC, an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level. In this book, two different models of a processor core, whose instruction set architecture is compatible with TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the SoC designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. Moreover, original CRC programs are used to verify the processor cores. SystemC to hardware flow is also illustrated by synthesizing the ALU part of the processor into a Xilinx-based hardware.

Product Specifications

Brand: VDM Verlag
Format: paperback
ASIN: 3639130359
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Release Date: 22 March 2009
Listed Since: 02 April 2009

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VDM Verlag SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE

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