Springer Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate (Analog Circuits and Signal Processing)

Product Description This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific protections. From the Back Cover This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections. About the Author Pietro Buccella is a postdoctoral researcher at EPFL in Lausanne, Switzerland. He received the Ph.D. degree in microsystems and microelectronics from EPFL, Switzerland (’16), the M.Sc. degree in electronic engineering from the Polytechnic University of Turin, Italy (’05). From 2005 to 2010, he was an analog IC design engineer at Microchip Technology Switzerland working in the field of sensor interface, high-voltage and power management CMOS integrated circuit design. From 2010 to 2012, he was a security engineer at Kudelski Group, testing the hardware security of microcontroller and smartcard chips. His main research interests include sensor interface, power management and mixed-signal HV IC design. Camillo Stefanucci is an affiliated research scientist at the École Polytechnique Fédérale de Lausanne (EPFL, Switzerland). He received the Ph.D. degree in Microelectronics from  EPFL, Switzerland (’16),  the M.Sc. degree in electronic engineering from the Polytechnic University of Milan, Italy (’12) and the joined M.Sc. degree in Nanotechnologies from the Polytechnic University of Turin, Italy and the Institut National Polytechnique de Grenoble, France  (’11). He has experience as analog IC