Springer Turbo-like Codes: Design for High Speed Decoding

Product Description This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps). From the Back Cover The advent of turbo codes has sparked tremendous research activities around the theoretical and practical aspects of turbo codes and turbo-like codes. The crucial novelty in these codes is the iterative decoding. Turbo-like Codes introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus of Turbo-like Codes is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps). In this book a novel high-speed turbo decoder is presented that exploits parallelization. Parallelism is achieved very efficiently by exploiting the flexibility of message-passing algorithm. It has been shown that very large speed gains can be achieved by this scheme while the efficiency is maintained reasonably high. Memory access, which poses a practical problem for the proposed parallel turbo decoder, is solved by introducing the conflict-free interleaver. The latency is further improved by designing a special kind of conflict-free interleaver. Furthermore, an algorithm to design such interleaver is presented. It is shown that the performance of turbo code is not sacrificed by using the interleaver with the proposed structure. Although turbo code has near Shannon-capacity performance and the proposed architecture for parallel turbo decoder provides a very efficient and highly regular hardware, the circuit is still very complex and demanding for very high-speed decoding. Therefore, the next step would be finding turbo-like codes that not only achieve excellent error correction capability, but also are very simple. As a result, a class of new Low-Density Parity-Check (LDPC) codes for different rates and block-sizes, called Accumulate-Repeat-Accumulate (ARA) codes, is presented. The performance of ARA codes is analyzed and shown that some ARA codes perform very close to random codes, which achieve Shannon limit.