Architectures for High Dynamic Range CMOS Pipeline ADC conversion - Image 1

£60.00

LAP Lambert Academic Publishing Architectures for High Dynamic Range CMOS Pipeline ADC conversion

Name: Architectures for High Dynamic Range CMOS Pipeline ADC conversion
Brand: LAP Lambert Academic Publishing
Price: 60.0 GBP
Availability: InStock

Electronics Engineering

Price data last checked 12 day(s) ago - will refresh soon

View at Amazon

We'll watch every seller, every day. One email when your price arrives.

It has never been this cheap. We have no record of a lower price.

£60 today · cheaper than every other day in the last 3 months

NEW HERE?

Amazon shows you one price. We show you all of them.

Tosheroon watches Amazon prices so you don't have to. Every product on Amazon has a price history — we make it visible. Set the price you'd actually pay, and we'll email you the second it gets there. No app, no account, one email.

WHAT'S ON THIS PAGE

↓ Price chart
when this has been cheap or pricey

↓ Forecast
where the price is heading next

↓ Statistics
all-time high & low, recent range

↑ Price alert
name your number, we'll email you

Price History & Forecast

Grey patches = out of stock. Cheaper = lower on the chart. Hover for exact prices.

Last 79 days • 79 data points (No recent data available)

Historical

Generating forecast...

Price Distribution

Price distribution over 79 days • 1 price levels

Days at Price

Price Analysis

Most common price: £60 (79 days, 100.0%)

Price range: £60 - £60

Price levels: 1 different prices over 79 days

Description

This book addresses the study of high dynamic range pipeline A/D (Analogue-to-Digital) data converters architectures suitable for data communications. Two different circuit architectures are proposed, with a common goal of obtaining a high dynamic range characteristic. The first architecture consists on a classical pipeline A/D converter with an input dynamic range in the order of 80 dB. The second architecture consists of a pipeline A/D converter with non-linear input-output transfer characteristics, of the logarithmic type, capable of reaching the same dynamic range of 80 dB. New architectures are developed based on their linear counterparts, where the linear signal operations was replaced by their equivalents in the logarithmic domain. Digital error correction and calibration techniques, traditionally used in linear converters, are extended to the logarithmic case. A method to analyze errors in the class of logarithmic converters is also presented. Finally, the design and experimental characterization of two integrated circuits, one for each type of the developed architectures, are presented to assess the practical feasibility of the proposed solutions.

Product Specifications

Brand: LAP Lambert Academic Publishing
Format: paperback
ASIN: 6139884047
Category: Books > Subjects > Science, Nature & Maths > Engineering & Technology > Electronics & Communications Engineering > Electronics Engineering
Domain: Amazon UK
Release Date: 01 August 2018
Listed Since: 18 August 2018

Barcode

No barcode data available

LAP Lambert Academic Publishing Architectures for High Dynamic Range CMOS Pipeline ADC conversion

It has never been this cheap. We have no record of a lower price.

Price History & Forecast

Price Distribution

Price Analysis

Description

Product Specifications

Barcode

Similar Products You Might Like

Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters

Digitally Assisted Pipeline ADCs: Theory and Implementation

Reference-Free CMOS Pipeline Analog-to-Digital Converters (Analog Circuits and Signal Processing)

Advanced Data Converters

Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

Dynamic Translinear and Log-Domain Circuits: Analysis and Synthesis: 481 (The Springer International Series in Engineering and Computer Science, 481)

Systematic Design for Optimisation of Pipelined ADCs: 607 (The Springer International Series in Engineering and Computer Science, 607)

Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

Concept and Design of a High Speed Current Mode Based SAR ADC

Static and Dynamic Performance Limitations for High Speed D/A Converters: 761 (The Springer International Series in Engineering and Computer Science, 761)

Mm-wave CMOS Phase-Locked Loops

Low-Voltage CMOS Log Companding Analog Design: 733 (The Springer International Series in Engineering and Computer Science, 733)

Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission (Analog Circuits and Signal Processing)

Smart AD and DA Conversion (Analog Circuits and Signal Processing)

Background Calibration of Time-Interleaved Data Converters (Analog Circuits and Signal Processing)

A Reconfigurable Low Noise Amplifier for a Multi-standard Receiver: A Reconfigurable Low Noise Amplifier for a Multi-standard Receiver

Real Time Digital Signal Processing in Power Systems using FPGAs: An Analysis of Time-Varying Waveform Distortions and Power Disturbances

Static and Dynamic Performance Limitations for High Speed D/A Converters: 761 (The Springer International Series in Engineering and Computer Science, 761)

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing: Advances in Analog Circuit Design 2014

Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies: 28 (Springer Series in Advanced Microelectronics, 28)

Highly Linear Integrated Wideband Amplifiers: Design and Analysis Techniques for Frequencies from Audio to RF: 490 (The Springer International Series in Engineering and Computer Science, 490)

Time-interleaved Analog-to-Digital Converters (Analog Circuits and Signal Processing)