£43.00

Südwestdeutscher Verlag für Hochschulschriften Spezifikation, Simulation und Validierung von Prozessoren: Spezifikation auf einem hohen Abstraktionsniveau, modellbasiertes Testen, dynamische Validierung, Simulation

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Description

In vielen Bereichen werden Spezialanwendungen mit hohen Ansprüchen an die Hardware entwickelt. Dabei ist es sinnvoll, neben der Software- und Compileroptimierung auch die Prozessoren zu optimieren. Dieses Buch trägt dazu bei, die Entwickler bei dem Entwurf von Prozessoren zu unterstützen. Das für diesen Zweck entwickelte Werkzeugsystem beschreibt die visuelle domänenspezifische Sprache ViCE-UPSLA für den Entwurf von Prozessoren. Mittels integrierter Generatoren im Werkzeugsystem können wahlweise zyklengenaue Mikroarchitektur- oder Instruktionssatzsimulatoren aus einer Spezifikation vollständig generiert werden. Ein weiterer Schwerpunkt dieses Buches liegt in der Validierung der Entwürfe. Die dynamischen Validierungsmethoden greifen die Konzepte aus dem modellbasierten Testen auf, indem aus der Prozessorspezifikation Testfälle für die dynamische Validierung automatisch generiert werden. Für Entwurf und Bearbeitung der Testfälle wird eine weitere visuelle Spezifikationssprache vorgestellt. Die Sprache sowie die Methoden zur automatischen Testfallgenerierung werden in diesem Buch erläutert.

Product Specifications

Format
paperback
Domain
Amazon UK
Release Date
19 September 2013
Listed Since
26 October 2013

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