LAP Lambert Academic Publishing Modeling and Simulation of ARM Processor Architecture: Using SystemC

A software model of processor core created using HDL can serve as the master device to verify functionalities of various slave devices. The hard model available from the manufacture may not be flexible & compatible with the software platform for the verifications. This book presents ARM Cortex- M3 processor model generated with the help of a modeling and verification tool like SystemC having inbuilt functions to reduce coding complexity. ARM Cortex – M3 is a 32-bit RISC processor based on Thumb-2 core technology, which enhances performance with higher code densities. Increasing demand of high-end embedded applications such as mobile phones with space, power and cost constraints prefer RISC architecture against CISC. ARM architecture has made instructions simpler with fixed- length and easy pipelining in order to achieve single clock cycle throughput even at higher frequencies.