Springer Beyond-CMOS Technologies for Next Generation Computer Design

This book describes the bottleneck faced soon by designers of traditional CMOS devices, due to device scaling, power and energy consumption, and variability limitations. This book aims at bridging the gap between device technology and architecture/system design. Readers will learn about challenges and opportunities presented by “beyond-CMOS devices” and gain insight into how these might be leveraged to build energy-efficient electronic systems. From the Back Cover This book describes the bottleneck faced soon by designers of traditional CMOS devices, due to device scaling, power and energy consumption, and variability limitations. This book aims at bridging the gap between device technology and architecture/system design. Readers will learn about challenges and opportunities presented by “beyond-CMOS devices” and gain insight into how these might be leveraged to build energy-efficient electronic systems. Provides an overview of CMOS scaling challenges and motivation for considering “beyond-CMOS devices;” Discusses challenges posed by beyond-CMOS integration; Sheds light on how device architecture and systems should be designed differently leveraging beyond-CMOS device technologies. About the Author Rasit O. Topaloglu works on next generation computer design at IBM. After internships at Nortel Networks, Alcatel Microelectronics, and Qualcomm, since 2005 he has worked at AMD, GLOBALFOUNDRIES and IBM. He obtained his B.S. in Electrical&Electronic Engineering at Bogazici University, M.S. and Ph.D. at University of California San Diego in Computer Science and Engineering. He has 20 issued US patents covering semiconductor devices and interconnects and around fifty international publications. He has a best paper award at ISQED. He serves as a technical advisory board member at Semiconductor Research Corporation for IBM. He has served in the technical program committees of DAC, DATE, ICCAD, ISPD, ISQED, and SLIP. He served as the General Chair of ACM/IEEE DAC Workshop on Design Automation for Beyond-CMOS Technologies in 2015. He edited More than Moore Technologies in Next-Generation Computer Design, Springer, 2015. He is an IEEE Senior Member.   H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering. He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center.   At IBM, he held various positions from Research Staff Member to Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology. During his time at IBM, he managed pathfinding research on high-k/metal gate, strained silicon, alternative channel materials such as Ge and III-V, multi-gate FinFET, ultra-thin SOI – many of these have now become product technology at various companies.  Professor Wong’s research aims at translating discoveries in science into practical technologies. His works have contributed to advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging. His present research covers a broad range of topics including carbon electronics, 2D layered materials, wireless implantable biosensors, directed self-assembly, device modeling, brain-inspired computing, non-volatile memory, and monolithic 3D integration. He is a Fellow of the IEEE. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford