Springer VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip

Review From the reviews:“An academic project of developing an application-specific VLSI architecture for H.264/AVC video encoding is described in the book. … The book addresses to researchers, educators, and developers in video coding systems, hardware accelerators for image/video processing, and high-level synthesis of VLSI. Especially, those who are interested in state-of-the-art parallel architecture and implementation of intra prediction, integer motion estimation, fractional motion estimation, discrete cosine transform, context-adaptive binary arithmetic coding, and deblocking filter will find design ideas from this book.” (Eleonor Ciurea, Zentralblatt MATH, Vol. 1191, 2010) Product Description High definition video requires substantial compression in order to be transmitted or stored economically. This volume presents VLSI design and chip implementation for high definition H.264/AVC video encoding using a state-of-the-art video application. From the Back Cover Back Cover CopyVLSI Design for Video CodingBy:Youn-Long LinChao-Yang KaoJian-Wen ChenHung-Chih KuoHigh definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.• Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;• Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;• Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;