£73.75

Springer Formal Semantics and Proof Techniques for Optimizing VHDL Models

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Description

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Product Specifications

Format
paperback
Domain
Amazon UK
Publication Date
26 October 2012
Listed Since
27 March 2013

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