Academic Press Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures

CRC Press VLSI Architectures for Modern Error-Correcting Codes

CRC Press

Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design (IEEE Press)

Wiley-IEEE Press

From Algorithms to Hardware Architectures: Using Digital Radios as a Design Example

Springer

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability (IEEE Press)

Wiley

Wireless Receiver Architectures and Design: Antennas, RF, Synthesizers, Mixed Signal, and Digital Signal Processing

Academic Press

Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems (Analog Circuits and Signal Processing)

Springer

Energy Efficient Computing & Electronics: Devices to Systems (Devices, Circuits, and Systems)

CRC Press

Adapted Compressed Sensing for Effective Hardware Implementations: A Design Flow for Signal-Level Optimization of Compressed Sensing Stages

Springer

Implementing Software Defined Radio

Springer

Coding Theory: Algorithms, Architectures and Applications

Wiley

Deep Learning Systems: Algorithms, Compilers, and Processors for Large-Scale Production (Synthesis Lectures on Computer Architecture)

Springer

Digital Design of Signal Processing Systems: A Practical Approach

Wiley

Dedicated Digital Processors: Methods in Hardware/Software Co-Design

Wiley

High-Speed Decoders for Polar Codes

Springer

High-Speed Decoders for Polar Codes

Springer

Reconfigurable System Design and Verification

CRC Press

Advanced FPGA Design: Architecture, Implementation, and Optimization (IEEE Press)

Wiley

High-Performance and High-Speed Pipelined ADCs (Synthesis Lectures on Engineering, Science, and Technology)

Springer

Low-Power CMOS Design for Wireless Transceivers

Springer

Real-Time Heterogeneous Video Transcoding for Low-Power Applications

Springer

Real-Time Heterogeneous Video Transcoding for Low-Power Applications

Springer

Low Power Modem Design: A guidance to use novel algorithms (QPSK) and digital filters (FIR, IIR) with MATLAB, SIMULINK with VHDL and Xilinx FPGA

LAP Lambert Academic Publishing

Efficient Processing of Deep Neural Networks (Synthesis Lectures on Computer Architecture)

Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs

Springer